PIC18F1230T-I/SO【PDF 239/318 页】IC PIC MCU FLASH 2KX16 18SOIC

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Sheet目录3871

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2009 Microchip Technology Inc.

DS39758D-page 313

PIC18F1230/1330

Timer1 .............................................................................. 111

16-Bit Read/Write Mode ........................................... 114

Associated Registers ............................................... 115

Interrupt .................................................................... 114

Operation ................................................................. 112

Oscillator .......................................................... 111, 113

Oscillator Layout Considerations ............................. 113

Overflow Interrupt .................................................... 111

TMR1H Register ...................................................... 111

TMR1L Register ....................................................... 111

Use as a Clock Source ............................................ 113

Use as a Real-Time Clock ....................................... 114

Timing Diagrams

A/D Conversion ........................................................ 293

Asynchronous Reception ......................................... 161

Asynchronous Transmission .................................... 158

Asynchronous Transmission (Back-to-Back) ........... 158

Automatic Baud Rate Calculation ............................ 156

Auto-Wake-up Bit (WUE) During Normal Operation 162

Auto-Wake-up Bit (WUE) During Sleep ................... 162

BRG Overflow Sequence ......................................... 156

Brown-out Reset (BOR) ........................................... 289

CLKO and I/O .......................................................... 288

Clock/Instruction Cycle .............................................. 55

Dead-Time Insertion for Complementary PWM ....... 135

Duty Cycle Update Times in Continuous Up/Down Count

Mode ................................................................ 132

Duty Cycle Update Times in Continuous Up/Down Count

Mode with Double Updates .............................. 133

Edge-Aligned PWM .................................................. 132

EUSART Synchronous Receive (Master/Slave) ...... 291

EUSART Synchronous Transmission (Master/Slave) ....

291

External Clock (All Modes Except PLL) ................... 286

Fail-Safe Clock Monitor ............................................ 206

Low-Voltage Detect Characteristics ......................... 283

Low-Voltage Detect Operation ................................. 189

Override Bits in Complementary Mode .................... 139

PWM Output Override Example #1 .......................... 141

PWM Output Override Example #2 .......................... 141

PWM Period Buffer Updates in Continuous Up/Down

Count Modes ................................................... 130

PWM Period Buffer Updates in Free-Running Mode 130

PWM Time Base Interrupt (Free-Running Mode) .... 126

PWM Time Base Interrupt (Single-Shot Mode) ........ 127

PWM Time Base Interrupts (Continuous Up/Down Count

Mode with Double Updates) ............................ 128

PWM Time Base Interrupts (Continuous Up/Down Count

Mode) ............................................................... 127

Reset, Watchdog Timer (WDT), Oscillator Start-up Timer

(OST), Power-up Timer (PWRT) ...................... 289

Send Break Character Sequence ............................ 163

Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)

............................................................................ 45

Start of Center-Aligned PWM ................................... 133

Synchronous Reception (Master Mode, SREN) ...... 166

Synchronous Transmission ...................................... 164

Synchronous Transmission (Through TXEN) .......... 165

Time-out Sequence on POR w/PLL Enabled (MCLR Tied

to VDD) ............................................................... 45

Time-out Sequence on Power-up (MCLR Not Tied to

VDD, Case 1) ...................................................... 44

Time-out Sequence on Power-up (MCLR Not Tied to

VDD, Case 2) ...................................................... 44

Time-out Sequence on Power-up (MCLR Tied to VDD,

VDD Rise < TPWRT) ............................................ 44

Timer0 and Timer1 External Clock .......................... 290

Transition for Entry to Idle Mode ............................... 36

Transition for Entry to SEC_RUN Mode .................... 33

Transition for Entry to Sleep Mode ............................ 35

Transition for Two-Speed Start-up (INTOSC to HSPLL)

204

Transition for Wake From Idle to Run Mode .............. 36

Transition for Wake From Sleep (HSPLL) ................. 35

Transition from RC_RUN Mode to PRI_RUN Mode .. 34

Transition from SEC_RUN Mode to PRI_RUN Mode

(HSPLL) ............................................................. 33

Transition to RC_RUN Mode ..................................... 34

Timing Diagrams and Specifications ............................... 286

CLKO and I/O Requirements ................................... 288

EUSART Synchronous Receive Requirements ....... 291

EUSART Synchronous Transmission Requirements ....

291

External Clock Requirements .................................. 286

PLL Clock ................................................................ 287

Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-

er-up Timer and Brown-out Reset Requirements ..

289

Timer0 and Timer1 External Clock Requirements ... 290

Top-of-Stack Access .......................................................... 52

TSTFSZ ........................................................................... 255

Two-Speed Start-up ................................................. 191, 2 04

Two-Word Instructions

Example Cases ......................................................... 56

TXSTA Register

BRGH Bit ................................................................. 151

Voltage Reference Specifications .................................... 282

Watchdog Timer (WDT) ........................................... 191, 2 02

Associated Registers ............................................... 203

Control Register ....................................................... 202

During Oscillator Failure .......................................... 205

Programming Considerations .................................. 202

WWW Address ................................................................ 314

WWW, On-Line Support ...................................................... 7

XORLW ........................................................................... 255

XORWF ........................................................................... 256

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